A Scalable and Adaptive Network on Chip for Many-Core Architectures

The continuous observance of Moore’s law has enabled to continuously implement increasingly powerful single-core processors than in the past. The increase of clock frequency and complexity of the microarchitecture were previously the main means enabling this performance enhancement. However, physical and architectural limitations necessitated a rethinking in recent times. Instead of increasing the performance of a single core, the number of cores is elevated today in order to enhance the computing power of a system. This concept of multi-core and many-core architectures enables to increase the performance almost linearly with the number of cores. However, existing bus-based communication infrastructures emerged as a limiting factor for this method of performance increase. Consequently, networks on chip have been proposed to create scalable many-core processor systems with respect to communication. Inspired by these developments, a network on chip based communication infrastructure is presented in this work. In order to simplify and accelerate the design of future many-core systems, a modular simulator-based evaluation and design methodology for networks on chip is introduced. As a basis for the proposed modular communication system, a scalable state of the art network on chip is developed in this work. This network is extended by novel mechanisms for quality of service, self-optimization and fault tolerance. In the context of quality of service, a novel approach for run-time adaptive bandwidth reservation, for end-to-end connections is proposed. It enables adjustable, hard guarantees for throughput and latency. An approach for region-based allocation of communication resources, enables run-time establishment of virtual networks in order to isolate the communication of individual applications. Novel self-optimization strategies are intended to increase the performance of the network and optimize its power consumption without necessitating complex software management. An innovative approach for detection, localization and treatment of permanent errors prepares the presented network on chip architecture for future technologies; with such errors being expected to occur frequently. With these aspects and concepts, this work provides a thorough and flexible approach for scalable communication in future many-core processor systems.